1. Field of the Invention
Example embodiments of the present invention relate generally to a sub word-line driver and method thereof, and more particularly to a layout structure for a sub word-line driver and method thereof.
2. Description of the Related Art
A memory cell array of a conventional semiconductor memory device may be divided into four memory banks, with each memory bank divided into a plurality of memory blocks. Each memory block may be divided into a plurality of sub array blocks. Higher integration memory cell arrays may employ a word line driver structure having a plurality of sub word line drivers. The sub word line drivers may be positioned between adjacent sub array blocks in order to reduce a delay (e.g., an interconnect delay) by a line load of the word line due to an elongated interconnect length.
For example, in a semiconductor memory device having 256 megabits (Mb) of memory capacity, a memory cell array may be divided into four memory banks, with each memory bank having 32 memory blocks positioned in a longitudinal direction of a chip (e.g., a semiconductor memory chip). Each of the memory blocks may have 16 sub array blocks in a width direction of the chip. The sub word line drivers may be positioned between the sub array blocks.
FIG. 1 illustrates an array of sub array blocks and sub word line drivers in a conventional semiconductor memory device. Referring to FIG. 1, the conventional semiconductor memory device may include a plurality of sub array blocks (SBs) 20 and a plurality of sub word line driver blocks (SWDBs) 10 positioned between the SBs 20.
At least one of the SBs 20 may include a plurality of memory cells, with each of the plurality of memory cells connected to a word line and a bit line. One of the SWDBs 10 may include a plurality of sub word line driver circuits (SWDs), which may be connected to the word lines, respectively, which may thereby be connected to the plurality of memory cells. Any of the word lines may be selected in response to input signals (Pxi0 to Pxi3).
FIG. 2 illustrates an array of a representative SWDB 10 of FIG. 1. Referring to FIG. 2, the SWDB 10 may include a plurality of SWDs. The sub word line drivers 12 and 14 may repeat in a lengthwise direction with respect to the bit line.
Referring to FIG. 2, an aligned (e.g., adjacent) pair of sub word line drivers 12 and 14 may be driven by the same input signal. The aligned pair of sub word line drivers 12 and 14 may be positioned at an upper or lower portion, respectively, in a lengthwise direction with respect the word line of the SBs 20 of FIG. 2.
Four word lines may be sequentially arranged as a first word line, a second word line, a third word line and a fourth word line. The first word line may be connected to the sub word line driver 12 positioned under the sub array block 20, the second word line may be connected to the sub word line driver 12 positioned above the sub array block 20, the third word line may be connected to the sub word line driver 14 positioned under the sub array block 20, and the fourth word line may be connected to the sub word line driver 14 positioned above the sub array block 20.
FIG. 3 is a circuit diagram illustrating an adjacent pair of the sub word line drivers 12 and 14 of FIG. 2. In an example, the sub word line drivers 12 and 14 of FIG. 2 may be representative of sub array blocks positioned either above or below a respective sub word line driver.
Referring to FIG. 3, the sub word line drivers 12 and 14 may receive first and second input signals A and B and may include first and second P-channel transistors P1 and P2 and first to fourth N-channel transistors N1, N2, N3 and N4. The sub word line driver 12 may include the first P-channel transistor P1, the first N-channel transistor N1 and the third N-channel transistor N3. The first P-channel transistor P1 may be connected between a conductive line connected to a power line and one of the plurality of word lines WL0 in a sub array block (e.g., sub array block 20). The first P-channel transistor P1 may be driven by the first input signal A. The power line may apply an external power voltage level VPP which may have a higher voltage level as compared to an internal power voltage VDD.
The first N-channel transistor N1 may be connected between the conductive line connected to the word line WL0 and a ground voltage. The first N-channel transistor N1 may be driven by the first input signal A. The third N-channel transistor N3 may be connected between the conductive line connected to the word line WL0 and the ground voltage. The third N-channel transistor N3 may be driven by the second input signal B.
The sub word line driver 14 may include the second P-channel transistor P2, the second N-channel transistor N2 and the fourth N-channel transistor N4. The second P-channel transistor P2 may be connected between a conductive line connected to a power line and a word line WL1 in the sub array block. The second P-channel transistor P2 may be driven by the first input signal A. The power line may apply an external power voltage level VPP which may have a higher voltage level as compared to an internal power voltage VDD.
The second N-channel transistor N2 may be connected between the conductive line connected to the word line WL1 and the ground voltage. The second N-channel transistor N2 may be driven by the first input signal A. The fourth N-channel transistor N4 may be connected between the conductive line connected to the word line WL1 and the ground voltage. The fourth N-channel transistor N4 may be driven by the second input signal B.
The first input signal A may enable the word lines WL0 and WL1 with an operation of the sub word line drivers 12 and 14 and the second input signal B may pre-charge the word lines. The sub word line drivers may be responsive to the same input signals (e.g., first and second input signals A and B) where only one word line may be enabled by PXi coding at any given time.
In conventional operation of the sub word line drivers 12 and 14, if at least one (e.g., one, both, etc.) of the first input signal A and the second input signal B are set to a first logic level (e.g., a higher logic level or logic “1”), the word line WL0 may be disabled (e.g., set to the ground voltage).
In conventional operation of the sub word line drivers 12 and 14, if the first input signal A and the second input signal B are set to a second logic level (e.g., a lower logic level), the external power voltage level VPP may be applied to the word line WL0 to enable the enable the word line WL0 (e.g., set to a voltage other than the ground voltage). The four sub word line drivers having the same input line may enable a single word line based on the input signals.
Conventional semiconductor memory devices having a sub word line driver structure as described above may have an increased layout area. Accordingly, reducing the layout area may be an important design characteristic.
As illustrated in FIGS. 2 and 3, the sub word line drivers 12 and 14 may be positioned between an “upper” sub array block 20 and a “lower” sub array block 20 in a lengthwise direction of the word lines. Conventional sub word line driver layout structures may have an increased layout area, thereby reducing an integration efficiency of semiconductor memory devices including the conventional sub word line drivers.